The present invention relates to an emulator and an emulation method which are capable of performing debug even in the case where the whole target system or a part thereof is not present and more particularly to a technology which is suitable for being applied to an emulator for a single chip microcomputer applied apparatus for example.
An emulator enables system debug or software debug to be performed while emulating a system which is an object of debug (i.e., a target system) with a microcomputer for emulation. Therefore, before the completion of the target system, it is difficult to perform the software debug for supporting an exchange of a signal between an I/O apparatus of the target system and the microcomputer is supported to be executed, or the total system debug covering the whole system. As a result, it is necessary to rely on the completion of the practical system as a target system.
A technology relating to a connection between an emulator and a microcomputer circuit board is disclosed in the U.S. Pat. No. 4,084,869. As a technology relating an emulator for emulating a target, and for enabling emulation to be performed without provision of a target system, there are proposed articles "HMCS 400-Series Emulator Unit: User's Manual; 1991, pp. 181" and "HMCS 400-Series Microcomputers: User's Manual; 1989, pp. 49", and JP-A-64-41938 (the term "JP-A" used herein means that the patent application was laid open to public inspection but has not been examined) and JP-A-62-173539. The technique described in JP-A-64-41938 is designed in such a way that when detecting an input instruction for a microcomputer for emulation, pattern data are generated to be directly supplied to the microcomputer for emulation while updating addresses of a memory for holding an input pattern, and when detecting an output instruction therefor, output pattern data from the microcomputer for emulation are written to a data memory while updating addresses of the data memory for holding output data. The technique described in JP-A-62-173539 is designed in such a way that pattern data are stored in an emulation memory in which addresses are updated in sequence every bus cycle of a microcomputer for emulation, and the pattern data are supplied in sequence to the microcomputer for emulation whenever the bus cycle is started.
However, each of the above-mentioned prior art systems is arranged in such a way that the pattern data are mechanically outputted in regular order to the microcomputer for emulation using the detection result of the input instruction or the start of the bus cycle as a trigger. Therefore, the order of output of the data must be previously determined and the determination result must be stored in the memory. For that purpose, it is necessary to predict the operation flow of the microcomputer for emulation. Therefore, with respect to the operation which deviated from the flow thus predicted, it is impossible to perform the emulation. For example, in the case where an interrupt routine, a conditional branch, or the like is present in the operation flow of the microcomputer for emulation, it is substantially impossible to predict an external interruption or the like which occurs asynchronously. Then, if an input instruction contrary to the prediction, the normal emulation can be performed no longer. With the arrangement as well in which the pattern data are supplied every bus cycle of the CPU, similarly, if an interruption occurs at a timing other than the predicted timing, or a branch contrary to the prediction occurs, the emulation cannot be performed. As a result, even if the emulation can be performed without provision of the target system, such emulation can be performed by only treating a range in which the number of steps capable of being emulated is very small so as to enable the operation flow to be surely predicted, as a unit.